Job Description:
As a DFT, you will work with chip architects, chip designers, implementation engineers and test engineers to define the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed-signal and digital VLSI designs. Then you’ll ensure it becomes reality. We’re doing a grounds-up implementation of new chip architecture, so you’ll have to ability to affect a new design.

Minimum qualifications:
1. BA/BS degree in Electrical/Computer Engineering with 5+ years of practical experience
2. Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
3. Experience with ASIC test, DFT, and debug
4. 5+ years of practical experience with test or DFT
5. Preferred qualifications
6. Experience using the Tessent tools
7. Hands-on expertise with commercial test generation tools for large complex designs
8. Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST
9. Experience with RTL simulation, synthesis and back end implementation flows
10. Experience defining and implementing MBIST engines
11. Experience running test compression software
12. Lab and test floor experience with real silicon
13. Experience trading off test options with product performance and schedule requirements

Roles and Responsibilities:
1. Define test structures, debug structures, test plans
2. Create test vectors or oversee their creation
3. Collaborate with physical design team to close requirements
4. Validate DFT requirements are being met
5. Work with designers to increase test coverage, debug observability and flexibility
6. Verify post-PD designs meet DFT requirements
7. Work with test personnel, stepping in to do run tests when needed